
LIBRARY ieee;library mylib;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use mylib.definitions.all;

ENTITY TestPabloRuiz_vhd IS
END TestPabloRuiz_vhd;

ARCHITECTURE behavior OF TestPabloRuiz_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT controlUnit
	PORT(
		clk_i : IN std_logic;
		clr_i : IN std_logic;
		int_req : IN std_logic;
		data_ack_i : IN std_logic;
		instr_ack_i : IN std_logic;
		port_ack_i : IN std_logic;
		opcode_in : IN std_logic_vector(3 downto 0);
		opcode_comp_in : IN std_logic_vector(1 downto 0);
		cod_ext3_in : IN std_logic_vector(2 downto 0);          
		proc_state : OUT processor_state;
		reg_file_we : OUT std_logic;
		PC_en : OUT std_logic;
		enable_IR : OUT std_logic;
		enable_acc : OUT std_logic;
		enable_data : OUT std_logic;
		is_immediate : OUT std_logic;
		is_branch : OUT std_logic;
		is_jump : OUT std_logic;
		is_misc : OUT std_logic;
		is_reti : OUT std_logic;
		is_load : OUT std_logic;
		is_store : OUT std_logic;
		is_alu : OUT std_logic;
		is_shift : OUT std_logic;
		is_in : OUT std_logic;
		is_ret : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_i :  std_logic := '0';
	SIGNAL clr_i :  std_logic := '0';
	SIGNAL int_req :  std_logic := '0';
	SIGNAL data_ack_i :  std_logic := '0';
	SIGNAL instr_ack_i :  std_logic := '0';
	SIGNAL port_ack_i :  std_logic := '0';
	SIGNAL opcode_in :  std_logic_vector(3 downto 0) := (others=>'0');
	SIGNAL opcode_comp_in :  std_logic_vector(1 downto 0) := (others=>'0');
	SIGNAL cod_ext3_in :  std_logic_vector(2 downto 0) := (others=>'0');

	--Outputs
	SIGNAL proc_state :  processor_state;
	SIGNAL reg_file_we :  std_logic;
	SIGNAL PC_en :  std_logic;
	SIGNAL enable_IR :  std_logic;
	SIGNAL enable_acc :  std_logic;
	SIGNAL enable_data :  std_logic;
	SIGNAL is_immediate :  std_logic;
	SIGNAL is_branch :  std_logic;
	SIGNAL is_jump :  std_logic;
	SIGNAL is_misc :  std_logic;
	SIGNAL is_reti :  std_logic;
	SIGNAL is_load :  std_logic;
	SIGNAL is_store :  std_logic;
	SIGNAL is_alu :  std_logic;
	SIGNAL is_shift :  std_logic;
	SIGNAL is_in :  std_logic;
	SIGNAL is_ret :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: controlUnit PORT MAP(
		clk_i => clk_i,
		clr_i => clr_i,
		int_req => int_req,
		data_ack_i => data_ack_i,
		instr_ack_i => instr_ack_i,
		port_ack_i => port_ack_i,
		opcode_in => opcode_in,
		opcode_comp_in => opcode_comp_in,
		cod_ext3_in => cod_ext3_in,
		proc_state => proc_state,
		reg_file_we => reg_file_we,
		PC_en => PC_en,
		enable_IR => enable_IR,
		enable_acc => enable_acc,
		enable_data => enable_data,
		is_immediate => is_immediate,
		is_branch => is_branch,
		is_jump => is_jump,
		is_misc => is_misc,
		is_reti => is_reti,
		is_load => is_load,
		is_store => is_store,
		is_alu => is_alu,
		is_shift => is_shift,
		is_in => is_in,
		is_ret => is_ret
	);

	clk_p : process
	begin
		wait for 50 ns;
		clk_i <= '0';
		
		wait for 50 ns;
		clk_i <= '1';	
	end process;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 50 ns;
--intrucciones
 		--opcode_in <= opc_mem_io_ld;
		opcode_in <= opc_mem_io_st;
		--opcode_in <= opc_mem_io_in;
		--opcode_in <= opc_mem_io_out;
		instr_ack_i <= '0';
		
		wait for 70 ns;
		instr_ack_i <= '1'; --para indicar que hay instruccion
		
		wait for 100 ns;
		instr_ack_i <= '0';
		--int_req <= '1';
		--data_ack_i<='1';
		data_ack_i<='0';
		--port_ack_i <= '1';
		--port_ack_i <= '0';
		--is_interrupt <='1';
		--is_interrupt <='0';
			

		wait for 200 ns;
		data_ack_i<='1';
		
		int_req <= '1';
		
		--port_ack_i <= '1';
      --clr_i <= '1';
	   --int_req <= '1';
		
		
		wait; -- will wait forever
	END PROCESS;

END;
